Arduino for STM32

And, now verified. Running until cycle counter reaches 0x80000000 results in the milllis timer reading 8951, resulting in a calculated clock frequency of 239.915008 Mhz, give or take the exactness of my time sampling. So, the clock driving the cycle counter IS 240 Mhz, and now I have a tool for meas...

I added *DWT_LAR = 0xC5ACCE55; // unlock (CM7) *SCB_DEMCR |= 0x01000000; *DWT_CYCCNT = 0; // reset the counter *DWT_CONTROL |= 1 ; // enable the counte and now it counts, now to find out how much in what time..... Thanks for the input ozcar.... Gullik AT32F403A Alive @ 240 Mhz Size register :1024 ID...

And, the indications of 80 Mhz are just set as a constant in boards.txt Changing it to 240 Mhz the printouts are reasonable, however I think clock should be calculated from the requested multiplication factor... and used crystal. Still we are back in the nS questions, nw to determine which timer del...

Hi ozcar Examinations of CTRL an CYCCNT First line is printout of F_CPU, which indicates 80 Mhz, trying to understand why PLL_MULT is 60 though, and pllclock 8 Mhz / 2 = 4 Both CTRL and CYCCNT are 0x40000000 The lonely 80 below the CYCCNT line is Serial.println(CYCLES_PER_MICROSECOND); which corresp...

I added the CYCCNT definition

A print of that gives

CYCCNT : 1073741824
0
CYCCNT : 1073741824
0
CYCCNT : 1073741824

i.e. it seems CYCCNT does not change. ( this is within the array dump routine, so the zero is milliseconds / loop which is currently about 32 uSec),
4096 * 8 nS.

My version of the manual is V2.02. The clock tree shows a gate connecting the output of APB1 or APB2 divider as input to timers. That signal says 240 Mhz max, but the clock it is taken from, is max 120 Mhz, so 120 Mhz is probably max. The maximum rate of 200 Mhz is probably a heritage from the 403 (...

Getting somewhere.....but still puzzled Modified code, sending 4 samples "unrolled" indicates there are transitions lasting approx. 16 nS. This is a multiple of 4.17 nS, i.e. 4 cycles to emit one word. So the instruction generated takes 16.66 nS. Thus it should be possible to generate data...

This is extremely confusing. The sample time is *very* close to 30 nS. This would imply a clock of 33 Mhz. I cannot derive such a clock from 240 Mhz, since that would imply a noninteger division.(7.2) There is no jitter to be seen on the output waveform, it is a continous sequence of 0 and 1 at 30 n...

Default setup in Arduino when selecting 60 as pll mult factor

PLL Multiplier = 59 (59+1=60, 60 * 4 Mhz) 240 Mhz
AHB divider = 0 (240 Mhz)
APB1 divider = 8 (120 Mhz)
APB2 divider = 8 (120 Mhz)

There is an AHB divider that allows you to run at PLLclock, /2, /4,/8,/16,/64,/128,/256 or /512 (but no /32 )

Gullik