Arduino for STM32

CMSIS definition from https://github.com/stm32duino/Arduino_Core_STM32/blob/main/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h I think this should be enough: // Write to register RNG -> CR = 0; RNG -> CR = (RNG -> CR ) | RNG_CR_RNGEN; // enable bit RNG -> CR |= RNG_CR_RNGEN; // enab...

Almoust as bluepill. Your board just don't have Timer4 compared to bluepill. But RM0008 apply to your board too.
I am not familiar wirh Roger's core DMA syntax, but i'm pritty sure there must some command to set lenght of DMA transfers ( for CNDTR register).

I was experiment with DMA to ODR, but with official core, and directly with registers. From what i understand, on bluepill, you can only use DMA1 to send either PortA or PortB, not both. In your example, dma_setup_transfer(DMA1, DMA_CH0, &GPIOA->regs->ODR, DMA_SIZE_16BITS, &dataA[step], DMA_...

Just4Fun wrote: ↑Tue Oct 04, 2022 5:17 pm It seems they are making an Arduino core for the W801 available!!!

See here.

Thank you for that link. I have W806 board that was waiting more than a year in the box
Blinking leds works !

I once found same thing in SdFat library, called "FreeStack.h" From that, simple sketch should work (at least at STM32F1/4): // from SDfat library extern "C" char* sbrk(int incr); // free RAM (actually, free stack inline uint32_t FreeBytes() { char top = 't'; return &top - re...

just 2 cents, if you are changing all the bits in one go, you may as well use ODR. for BSRR, to do the same, it may be 2 transactions, first reset all bits, then set the bits again separately. the alternate would be to do things like GPIOA->BSRR = value | (~ value << 16); I agree. In this case (R2R...

RM0368, page 161
In short, upper 16 bits of BSSR resets corresponding bits (1=reset, 0=don't change), and lower 16bit set corresponding bits (1=set, 0=don't change).
Set bits have priority over reset bits.
BSRR - Bit Set/Reset Register

To my understanding (as a hobby user) : setCaptureCompare is 0 indexed, CounterCompare Register (CCRx) is 0 indexed setOverflow is 1 indexed, Hardware AutoReload Register (ARR) is 0 indexed. setPrescaleFactor is 1 indexed, Prescaler register (PSC) is 0 indexed. To set duty cycle to 100% CounterCompa...

Hmmm, now even i am not sure anymore :lol: Goal was not to count cycles, but use setCaptureCompare to set 0% duty cycle with value 0, and 100% with value 255. And now i am not sure of that edge case. I think CounterCompare need to be greater than overflow to get 100% duty cycle. Overflow of 255 shou...

- use "pwmTim->setCaptureCompare(..." as first line of code in interrupt callback. No matter how long you calculations are, interrupt latency is usually same, so you'll have steady timing. Plus, once value of counter-compare is written, it will apply that value in next timer overflow. From...