AT32F403A anyone?

Anything not related to STM32
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

My version of the manual is V2.02. The clock tree shows a gate connecting the output of APB1 or APB2 divider as input to timers.

That signal says 240 Mhz max, but the clock it is taken from, is max 120 Mhz, so 120 Mhz is probably max.

The maximum rate of 200 Mhz is probably a heritage from the 403 (flat) which had a max of 200. I will try to enable a clock and see what comes out of
that experiment.

Gullik
ozcar
Posts: 143
Joined: Wed Apr 29, 2020 9:07 pm
Answers: 5

Re: AT32F403A anyone?

Post by ozcar »

The manual I was looking at before was just what Uncle Google turned up. From the page mentioned here by ag123, https://www.arterychip.com/en/product/AT32F403A.jsp, I find another manual, which says it is V2.03. The clock tree in this manual shows the 120MHz is multiplied by one or two, so 240MHz for TMRxCLK could be possible. I did not try to figure out what determines if the multiplication is by one or two though.

clock_tree.jpg
clock_tree.jpg (32.88 KiB) Viewed 17202 times

I also see that the timer counter register (timer base +0x24) which the old V1.06 manual called TMRx_CNT is now referred to as TMRx_CVAL. Who knows why they decided to change that?

I'm still curious about DWT. Do you know for sure that DWT does not provide cycle counter? What do you get for something like this:

Code: Select all

uint32_t CTRL = *((volatile uint32_t*)0xE0001000);
uint32_t CYCCNT = *((volatile uint32_t*)0xE0001004);
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

I added the CYCCNT definition

A print of that gives

CYCCNT : 1073741824
0
CYCCNT : 1073741824
0
CYCCNT : 1073741824

i.e. it seems CYCCNT does not change. ( this is within the array dump routine, so the zero is milliseconds / loop which is currently about 32 uSec),
4096 * 8 nS.
ozcar
Posts: 143
Joined: Wed Apr 29, 2020 9:07 pm
Answers: 5

Re: AT32F403A anyone?

Post by ozcar »

1073741824 = 0x40000000 which looks like a plausible reset value for CTRL, so is that DWT_CTRL (at 0xE0001000) or DWT_CYCCNT (at 0xE0001004) that you are showing there?

If that is really CYCCNT, what is in CTRL? That could indicate if the cycle counter is truly not implemented, or maybe (more likely, I hope) not enabled. You could just try to enable it with:

Code: Select all

*((volatile uint32_t*)0xE0001000) |= 1; // low order bit is "cycle counter enable"
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

Hi ozcar

Examinations of CTRL an CYCCNT

First line is printout of F_CPU, which indicates 80 Mhz, trying to understand why
PLL_MULT is 60 though, and pllclock 8 Mhz / 2 = 4

Both CTRL and CYCCNT are 0x40000000

The lonely 80 below the CYCCNT line is
Serial.println(CYCLES_PER_MICROSECOND);

which corresponds with the F_CPU value, but I believe this is bugs in the libcore for arduino.
I shall have a close look at these files to see if I understand. The timer used in delay() should clock CPU clock, if I can determine exactly
which clock that timer is inited with.....so it's value should be a good time/clock indication....

AHB clock field is 0 = not divided
APB1 & 2 div fields are both 8 which encodes HCLK/2 = 120 Mhz (??)
Thus timer clock should be 120 Mhz
--------------------------------------------------

AT32F403A Alive @ 80 Mhz
Size register :1024
ID register UID[31:0]: B4F0B7 [63:32] 2854C000 [95:64] 7C58710
CRM CTRL 3038E83
CRM CFG E02FE40A
CRM MISC3 D
PLL MULT : 60

AHB DIV : 0
APB1 DIV : 8
APB2 DIV : 8

IO ports status
CFGL CFGH IDT ODT SCR CCR WPR
GPIOA : 44444444 88844994 A4F3 A000 0 0 0
GPIOB : 44481111 44444444 9FB8 10 0 0 0
GPIOC : 44444444 44144444 0 0 0 0 0
IOMUX : 0 0 0 0 0 0 0
CRM_CTRL : @ : 40021000 3038E83 E02FE40A 0 0 0 14 421C 0 0 C000000
0
CTRL : 40000000
CYCCNT : 40000000
80
0
------------------------------------------
Then I add the cycle counter enable, CYCCNT does not change.
-----------------------------------------
CTRL : 40000000
CYCCNT : 40000000
CYCCNT : 40000000
80
0
-------------------------------------

Gullik
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

And, the indications of 80 Mhz are just set as a constant in boards.txt

Changing it to 240 Mhz the printouts are reasonable, however I think clock should be calculated from the requested multiplication factor...
and used crystal.

Still we are back in the nS questions, nw to determine which timer delay() and timer() uses

Gullik
ozcar
Posts: 143
Joined: Wed Apr 29, 2020 9:07 pm
Answers: 5

Re: AT32F403A anyone?

Post by ozcar »

webjorn wrote: Wed Sep 14, 2022 9:07 am
CTRL : 40000000
CYCCNT : 40000000
80
0
------------------------------------------
Then I add the cycle counter enable, CYCCNT does not change.
-----------------------------------------
CTRL : 40000000
CYCCNT : 40000000
CYCCNT : 40000000
80
0
-------------------------------------
0x40000000 for CTRL would indicate that the cycle counter is not enabled, which is as expected after reset. I'm not sure what to make of CYCCNT being the same, as it is supposed to be zeroed by reset.

With what I have done with STM32, both with and without STM32DUINO, I never had to enable the cycle counter, as I always found it was already enabled (DWT_CTRL = 0x40000001). I never tried to find out what enabled it, maybe some HAL initialisation?

But obviously you did not manage to enable it, as CTRL stays 0x40000000. Maybe updates to CTRL are protected by some song and dance you have to perform, but your Google-fu is as good as mine for checking that. I did do a quick test here on a STM32F103, and found I can turn the enable flag off and then back on again without doing anything else to somehow unlock access, but then it was enabled to begin with, and unfortunately I don't have an AT32 processor to try on.
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

I added

*DWT_LAR = 0xC5ACCE55; // unlock (CM7)
*SCB_DEMCR |= 0x01000000;
*DWT_CYCCNT = 0; // reset the counter
*DWT_CONTROL |= 1 ; // enable the counte

and now it counts, now to find out how much in what time.....
Thanks for the input ozcar....

Gullik


AT32F403A Alive @ 240 Mhz
Size register :1024
ID register UID[31:0]: B4F0B7 [63:32] 2854C000 [95:64] 7C58710
CRM CTRL 3038E83
CRM CFG E02FE40A
CRM MISC3 D
PLL MULT : 60

AHB DIV : 0
APB1 DIV : 8
APB2 DIV : 8

IO ports status
CFGL CFGH IDT ODT SCR CCR WPR
GPIOA : 44444444 88844994 A4FB A000 0 0 0
GPIOB : 44481111 44444444 FFB8 10 0 0 0
GPIOC : 44444444 44144444 0 0 0 0 0
IOMUX : 0 0 0 0 0 0 0
CRM_CTRL : @ : 40021000 3038E83 E02FE40A 0 0 0 14 421C 0 0 C000000
0
CYCCNT : 270AC1
0
CYCCNT : 4F5341
0
CYCCNT : 779BC1
0
CYCCNT : 9FE441
0
CYCCNT : C82CC1
0
CYCCNT : F07541
0
CYCCNT : 118BDC1
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

And, now verified.

Running until cycle counter reaches 0x80000000 results in the milllis timer reading 8951, resulting in a calculated
clock frequency of 239.915008 Mhz, give or take the exactness of my time sampling.

So, the clock driving the cycle counter IS 240 Mhz, and now I have a tool for measuring code.

Gullik
webjorn
Posts: 43
Joined: Sat Jul 09, 2022 8:49 pm

Re: AT32F403A anyone?

Post by webjorn »

My foggy understanding is clearing up......

"The result is a square wave on the pins, 30nS high and 30nS low, which equates to 16.67 Mhz, i.e. each sample 33 Mhz. It seems the cpu takes
5 instructions to write a word to GPIO. CPU clock is 240 Mhz as I have configured it. I would have hoped for a bit more than that but
this is as simple as it gets."

No, after examining 2000 writes on the scope, I can see that it takes 58 uS. This equates to 29 rather than 30 nS. The 29.166667 is actually
7 CPU cycles of 4.1666 nS, corresponding to 240 Mhz.

for(k=0;k<maxdata;k++) {
GPIOB->ODR = datarray[k];
}
-----resulting binary code----- after setting k = 0
80004c6: 3301 adds r3, #1
80004c8: f837 1b02 ldrh.w r1, [r7], #2
80004cc: 8191 strh r1, [r2, #12]
80004ce: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 // maxdata
80004d2: d1f8 bne.n 80004c6 <_Z4loopv+0x2aa>
------------------------
and it is indeed 7 instructions.

Thus it seems the highest programmed data speed (from an array) without DMA is 34.28 Mhz.
With this a simple hack would be a 16 channel logic analyzer at 1.5 times the speed of a $20 8-ch from ebay.
I cannot see any good way to unroll the loop since I need to change the array index, but I have to study ARM assmbler,
The ldrh.w and the strh could be replicated, but R7 needs to change.....+2 i guesss...

ldrh.w r1,[r7],#2
strh r1,[r2,#12]
adds r7,#2

this should be 4 instructions per move, so sampling should be 60 Mhz...

We'll see....

Gullik
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