NUCLEO-F756ZG: A0, A2 + ethernet

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quest4exit
Posts: 4
Joined: Sat May 07, 2022 6:47 am

NUCLEO-F756ZG: A0, A2 + ethernet

Post by quest4exit »

Hello,

I'm running into a strange problem and can't find a solution: I'm trying to use A0-A5 as OUTPUT-pins while having an mqtt client runnning.

Code: Select all

#include <LwIP.h>
#include <STM32Ethernet.h>

// this must be unique
byte mac[] = {0xDA,0x30,0xDE,0xEE,0xDE,0xEC};

// Enter an IP address for your controller below.
// The IP address will be dependent on your local network:
IPAddress ip(192, 168, 178, 177);
IPAddress gateway(192,168,178,1);
IPAddress subnet(255,255,255,0);

EthernetClient ethClient;

void setup() {

  pinMode(A2, OUTPUT); 
  pinMode(A0, OUTPUT); 

  Ethernet.begin(mac, ip);

 
}

void loop() {

  digitalWrite(A2, HIGH); 
  digitalWrite(A0, HIGH); 
  delay(500);   
  digitalWrite(A2, LOW); 
  digitalWrite(A0, LOW); 
  delay(500); 
  
}
Commenting the initialisation of the ethernet ("// Ethernet.begin(mac, ip);") makes everthing work, but as soon as I activate this line, LEDs connected to A0 and A2 just glow very softly and will not blink. All the other pins (A1, A3, A4 and A5) still work as they should.

I strongly suspect a problem with the PeripheralPins.c, but as far as I see, I commented all the possible colliding pin definitions:

Code: Select all

//*** ETHERNET ***

#ifdef HAL_ETH_MODULE_ENABLED
WEAK const PinMap PinMap_Ethernet[] = {
  //{PA_0,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS
  {PA_1,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_REF_CLK
  {PA_1_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_CLK
  // {PA_2,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDIO
  // {PA_3,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_COL   MSD 2022_05_14: Collision with A0 pin?
  {PA_7,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_CRS_DV
  {PA_7_ALT1, ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_DV
  {PB_0,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD2
  {PB_1,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD3
  // {PB_5,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT  MSD 2022-05-08 - Conflicts with SPI
  {PB_8,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
  {PB_10,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RX_ER
  {PB_11,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
  {PB_12,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0  MSD 2022-05-08: used by SPI for FRAM module
  {PB_13,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1  MSD 2022-05-08: used by SPI for FRAM module
  {PC_1,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_MDC
  {PC_2,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD2
  // {PC_3,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_CLK  MSD 2022_05_14: Collision with A2 pin?
  {PC_4,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD0
  {PC_5,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_RXD1
  {PE_2,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD3
  {PG_8,      ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_PPS_OUT
  {PG_11,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TX_EN
  // {PG_13,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD0
  // {PG_14,     ETH, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_ETH)}, // ETH_TXD1
  {NC,        NP,  0}
};
#endif 
Has anybody an idea, how to solve this problem?
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fpiSTM
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Answers: 91
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Re: NUCLEO-F756ZG: A0, A2 + ethernet

Post by fpiSTM »

Maybe a power issue ?

For Ethernet on this boards only those pins are required in PeripheralPins.c:
PA1 RMII Reference Clock
PA2 RMII MDIO
PC1 RMII MDC
PA7 RMII RX
PC4 RMII RXD0
PC5 RMII RXD1
PG11 RMII TX
PG13 RXII TXD0
PB13 RMII TXD1

all other can be commented.
quest4exit
Posts: 4
Joined: Sat May 07, 2022 6:47 am

Re: NUCLEO-F756ZG: A0, A2 + ethernet

Post by quest4exit »

"Maybe a power issue ?" - A good idea. But I had A1, A3, A4 and A5 working without problems.

"all other can be commented." - I even tried to comment all (!) the pins in the ethernet-section - with no effect. Maybe, there are different "default" pin definitions working somewhere in LwIP.h or STM32Ethernet.h?
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