STM32F401, F405, F407, f4xx? backup registers

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ag123
Posts: 697
Joined: Thu Dec 19, 2019 5:30 am
Answers: 2

STM32F401, F405, F407, f4xx? backup registers

Post by ag123 »

currently backup registers in the F4 libmaple (roger's and steve's) core don't seem to be reflecting the F4 backup registers
https://github.com/rogerclarkmelbourne/ ... bkp.h#L101

while attempting to use them, i ran into some bummers. the base address seemed inappropriate. Hence, i've made some changes in my local copy of bkp.h and bkp.c. Apparently on f401, f405, f407, f427 there are 20 backup registers. However, i'm not too sure about the rest.

bkp,h

Code: Select all

#define BKP_NR_DATA_REGS 20

/** Backup peripheral register map type. */
typedef struct bkp_reg_map {
    __IO uint32 DR1;            ///< Data register 1
    __IO uint32 DR2;            ///< Data register 2
    __IO uint32 DR3;            ///< Data register 3
    __IO uint32 DR4;            ///< Data register 4
    __IO uint32 DR5;            ///< Data register 5
    __IO uint32 DR6;            ///< Data register 6
    __IO uint32 DR7;            ///< Data register 7
    __IO uint32 DR8;            ///< Data register 8
    __IO uint32 DR9;            ///< Data register 9
    __IO uint32 DR10;           ///< Data register 10
    __IO uint32 DR11;           ///< Data register 11
    __IO uint32 DR12;           ///< Data register 12
    __IO uint32 DR13;           ///< Data register 13
    __IO uint32 DR14;           ///< Data register 14
    __IO uint32 DR15;           ///< Data register 15
    __IO uint32 DR16;           ///< Data register 16
    __IO uint32 DR17;           ///< Data register 17
    __IO uint32 DR18;           ///< Data register 18
    __IO uint32 DR19;           ///< Data register 19
    __IO uint32 DR20;           ///< Data register 20
} bkp_reg_map;

/** Backup peripheral register map base pointer. */
#define BKP                        ((struct bkp_reg_map*)(0x40002800 + 0x50))

/**
 * @brief Initialize backup interface.
 *
 * Enables the power and backup interface clocks, and resets the
 * backup device.
 */
__always_inline void bkp_init(void) {
    /* Don't call pwr_init(), or you'll reset the device.
	 * We just need the clock. */
    rcc_clk_enable(RCC_PWR);
    //rcc_clk_enable(RCC_BKP);
    //rcc_reset_dev(RCC_BKP);
}

/**
 * Enable write access to the backup registers.  Backup interface must
 * be initialized for subsequent register writes to work.
 * @see bkp_init()
 */
__always_inline void bkp_enable_writes(void) {
    *bb_perip(&PWR->CR, PWR_CR_DBP_BIT) = 1;
}

/**
 * Disable write access to the backup registers.
 */
__always_inline void bkp_disable_writes(void) {
    *bb_perip(&PWR->CR, PWR_CR_DBP_BIT) = 0;
}

uint32 bkp_read(uint8 reg);
void bkp_write(uint8 reg, uint32 val);

bkp.c

Code: Select all

/*
/*
 * returns data register address
 * reg is 1 to BKP_NR_DATA_REGS
 */
static __IO uint32* data_register(uint8 reg)
{
    if ( reg==0 || reg > BKP_NR_DATA_REGS) {
        return 0;
    }

    return (uint32*)BKP + reg - 1;
}

/**
 * Read a value from given backup data register.
 * @param reg Data register to read, from 1 to BKP_NR_DATA_REGS (10 on
 *            medium-density devices, 42 on high-density devices).
 */
uint32 bkp_read(uint8 reg) {
    __IO uint32* dr = data_register(reg);
    if (!dr) {
        ASSERT(0);                  /* nonexistent register */
        return 0;
    }
    return *dr;
}

/**
 * @brief Write a value to given data register.
 *
 * Write access to backup registers must be enabled.
 *
 * @param reg Data register to write, from 1 to BKP_NR_DATA_REGS (10
 *            on medium-density devices, 42 on high-density devices).
 * @param val Value to write into the register.
 * @see bkp_enable_writes()
 */
void bkp_write(uint8 reg, uint32 val) {
    __IO uint32* dr = data_register(reg);
    if (!dr) {
        ASSERT(0);                  /* nonexistent register */
        return;
    }
    *dr = val;
}
note that the above is code abstract for the main parts, it isn't the full file, there are other codes that's not included.
the above codes is working ok for me as far as accessing the registers goes.
it is necessary to call bkp_init(); prior to accessing RTC and the backup registers and
for writing use bkp_enable_writes() and bkp_disable_writes() while writing to the registers.
Last edited by ag123 on Wed Mar 03, 2021 4:00 pm, edited 2 times in total.
ag123
Posts: 697
Joined: Thu Dec 19, 2019 5:30 am
Answers: 2

Re: STM32F401, F405, F407, f4xx? backup registers

Post by ag123 »

it is quite interesting that on top of registers the bigger chips e.g. f405, f407, f427, f429 etc has in addition to registers 4KB backup sram.
while f401, f411 only has 20 backup registers. hence, it'd seem 20 backup registers is 'standard', but well i've not really review the rest of specs.
and in addition, those on stm32f103 are 16 bit backup registers, while those on stm32f4xx are 32bits registers. This is much more convenient as it can store a full int32 in each register.
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