STM32F103 SPI slave having to deal with a master that has SS active HIGH

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Y@@J
Posts: 57
Joined: Mon Sep 28, 2020 8:51 pm

STM32F103 SPI slave having to deal with a master that has SS active HIGH

Post by Y@@J »

Hi,

I have a problem with a /SS being a SS. The slave is a bluepill, the master sends data, formatted for a ST7920.
As is, I'm unable to read SPI data.
I inserted a CD40106 on the /SS line : success ! (CD40106 = inverter + Schmitt trigger, basically NOT-gates)
But I can't use it IRL !

My problem is that everything is on a PCB , and the inverter is a hack. I'm looking for a software only solution to this problem.

I already tried to disable SS ( SPI_SOFT_SS | SPI_SW_SLAVE ) in the SPISettings ctor, before calling SPI_2.beginTransactionSlave(), but no success. The reason is probably that data are sent as more or less even blocks of data, and the STM32 cannot decide when and how to start filling the buffer. And I want to read everything at once (1281 bytes)

I didn't find any flag allowing for an inverted SS (active HIGH).

I'm thinking of another solution.
- set SPI2_SS to another pin (I have some spare) ; let' call it new_NSS
- set an interrupt (set to CHANGE) to the default SPI2_SS (NSS2/PB12)
- when the PB12 ISR is triggered, read the PB12 state, and set another (output) pin to (! PB12 state)
- wire this pin to the new_NSS

I didn't try for now. It is uggly, but it requires minimal PCB hacking.

Do you know of a flag or something that could force SPI to consider SS HIGH instead of LOW ?

Here's a picture of the SPI data (WITH THE CD40106 HACK !) :

download/file.php?mode=view&id=762
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Last edited by Y@@J on Sat May 14, 2022 4:50 pm, edited 2 times in total.
Y@@J
Posts: 57
Joined: Mon Sep 28, 2020 8:51 pm

Re: STM32F103 SPI slave having to deal with a master that has SS active HIGH

Post by Y@@J »

I finally answer to myself :

https://www.st.com/resource/en/applicat ... ronics.pdf

page 2/24

STM32F1 : "Swap of MOSI/MISO, reversed SS logic " : NO :cry:
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