Clock enhancement for F401/11

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Bingo600
Posts: 82
Joined: Sat Dec 21, 2019 3:56 pm

Clock enhancement for F401/11

Post by Bingo600 »

Hi Steve

I just made a small enhancement to /STM32F4/cores/maple/libmaple/rccF4.c
I wanted it to automatically set 84 or 96MHz System clock(s) , based on the Compile define CRYSTAL_FREQ

I snipped your existing #ifdef from the 168MHz section , and used ag123's neat python script to find the right Clock constants.

Attached is a git diff against master , and the python script.

For the python script , edit it , and set HSE Clock + Lower/Upper search limit , and it will list PLL parms that matches (48MHz USB) within the limits.

pypll output

Code: Select all

bingo@T430s:~/1-Arm/stm32/stm32f4/STM32F411CEU6$ ./stm32f4-pll.py 
FHSE: 25 m: 25 n: 192 p: 2 (RCC_PLLP_DIV2) q: 4 fusb: 48.0 fcpu: 96.0
FHSE: 25 m: 25 n: 384 p: 4 (RCC_PLLP_DIV4) q: 8 fusb: 48.0 fcpu: 96.0
FHSE: 25 m: 50 n: 384 p: 2 (RCC_PLLP_DIV2) q: 4 fusb: 48.0 fcpu: 96.0
bingo@T430s:~/1-Arm/stm32/stm32f4/STM32F411CEU6$ 



bingo@T430s:~/1-Arm/stm32/stm32f4/STM32F411CEU6$ ./stm32f4-pll.py 
FHSE: 8 m: 1 n: 42 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 2 n: 84 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 3 n: 126 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 4 n: 168 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 5 n: 210 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 6 n: 252 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 7 n: 294 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 8 n: 336 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 9 n: 378 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 10 n: 420 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 11 n: 462 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
FHSE: 8 m: 12 n: 504 p: 4 (RCC_PLLP_DIV4) q: 7 fusb: 48.0 fcpu: 84.0
bingo@T430s:~/1-Arm/stm32/stm32f4/STM32F411CEU6$ 

Attachments
STM32F4-HSE-25-8-to-84-or-96MHz.tgz
(1.11 KiB) Downloaded 49 times

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