ADC sample rate of 5 Ms/s on bluepill STM32F103

[Pito]

Below is a simulation of the input circuitry and Sample and Hold of STM32F103 ADC.
Radc is 1k and Cadc is 8pF (Datasheet).

C1 is a parasitic capacity of the input pin and wiring.
Diodes and 200ohm resistor -> simplified PIN protection wiring inside the chip.

1. First picture is how the edges look like at the Cadc for Radc=1k 3k 10k.
It only shows the BW of the input circuitry.
For 1k it looks good.

The Sample and Hold is opened for a small fraction of the sampling period only, say 30ns at 5Ms/s. During this time the Cadc must charge/discharge itself via the resistors such the voltage at Cadc always follows the input voltage (it means at the end of the S&H the voltage at Cads should be as close as possible to the actual input voltage).

2. Next is the 1MHz sine 3Vpp input, ADC 5Msamples/s, Sample and Hold is opened for 30ns, sampling period 200ns.
It looks pretty good for "1MHz sine". The error could be something like 3% full scale max.

Of course, for full 3.3V squared input the Sample and Hold must be able to charge/discharge the Cadc within 30ns from 0 to 3.3V and vice versa, worst case.

[bit_factory]

Very good simulation pito. I think an error of 3% is accettable for my case.
Thank you for advices

[davidkleng]

bit_factory, can you post your code? I have been modifying the O-Scope too, doing some tests. Thre problem i have is that when I use

ADC_CR1_FASTINT = 0x7000;
ADC1->regs->CR1 |= ADC_CR1_FASTINT;

i have the same Samplig time when using dual regular simultaneous mode, reading 2 different pins:

ADC_CR1_REGSIMULTANEOUS = 0x6000;
ADC1->regs->CR1 |= ADC_CR1_REGSIMULTANEOUS;

In both cases, its 3584 uS for with 1024*6 samples.
According to the datasheet and your first post, it should be less when doing fast interleaved mode.