In case somebody is interested here the alpha for a new ArduinoCore-stm32wb: https://github.com/GrumpyOldPizza/ArduinoCore-stm32wb
This is not associated or derived from ST's maintained Arduino Core. It's heritage comes from the original SAMD core via STM32L4 code.
Why ? I like to play. Play with low power, play with async code, play with atomics, play with new concepts ...
So what does this code contain ?
- BLE, GAP PERIPHERAL, GATT SERVER; non-blocking; data length extension, encryption/authentication, secure connections, fixed pin, pairing, 1M/2M phy handling; mostly ArduinoBLE compatible, except where the latter one uses blocking concepts;
- PDM (and I2S); 4th order CIC followed by a 15 tap half band filter (alias removal), a 64 tap FIR (droop compensation), and a IIR (high pass, offset correction); some rather nifty assembly code there to study; 48kHz stereo is doable with a 64MHz CPU clock
- Tons of low power management; dynamic clock switching; SLEEP / STOP / STANDBY / SHUTDOWN; background code can cycle automatically between various variants of SLEEP/STOP; bus down clocking; clock gating of currently idle peripherals; BLE works with 32MHz and 64MHz (sadly not 16MHz)
- TimerMillis class for one-shot or periodic callbacks; done in a tickless manner, i.e. no periodic internal wakeups.
- RTC class supporting GPS time, UTC (with and without local timezone offset); derived from the original RTCZero class concept
- GNSS class with support for UBLOX based GNSS units; power management; PPS bridge to RTC for timesync; short term and long term offset/interval correction
- SFLASH (SPI NOR), either raw data accesses or via a FTL (file translation layer) to a FAT file system; bridge from there to USB/MSC, so that the SFLASH can be mounted from a laptop; wear leveling, garbage collection; the NOR parts are accessed via SPI or via QSPI.
- SDCARD via SPI; full CRC checking with retries; bridge to USB/MSC; latter one implemented as background process; measured data rate for USB/MSC is about 950kB/sec, raw file system throuput is close to 2MB/sec
- DOSFS, FAT12/FAT16/FAT32 file system with long file names; FAT caching, directory caching; full implementation of the spec
- USB/CDC with full support for interrupt endpoint driven serial state updates and break handling
- LPUART/USART support with wakeup from STOP (2/1), RTS/CTS handling plus XON/XOFF flow control; support for somewhat obscure settings to get for example those SBUS R/C receivers to work
- SPI with master and slave; DMA based async transfers (think about updating a part of TFT via SPI, while preparing some the next data buffer in parallel)
- EEPROM emulation in the main FLASH, with wear leveling (kind of complex, as CM4 and CM0+ need to be in sync there ...)
- Arduino IDE 2.0 support, with debugging via ST-Link ...
The BLE class is as always work in progress. I never ever get the API design right the first time around. So any feedback in terms of design, concepts, missing functionality, better way of exposing functionality and such are welcome. The code will go throu a few iterations, especially with OTA in mind. For the time being I'd like to keep it at GAP PERIPHERAL / GATT SERVER though, to iron out the kinks.
Ah, yes, the NUCLEO-WB55RG is supported, and yes, there is a sketch to upload/update FUS/BLE directly ...
