just reviewed stm32f103 rm0008
https://www.st.com/resource/en/referenc ... ronics.pdf
IN packets (data transmission)
When receiving an IN token packet, if the received address matches a configured and valid
endpoint one, the USB peripheral accesses the contents of ADDRn_TX and COUNTn_TX
locations inside buffer descriptor table entry related to the addressed endpoint. The content
of these locations is stored in its internal 16 bit registers ADDR and COUNT (not accessible
by software). The packet memory is accessed again to read the first word to be transmitted
(refer to Structure and usage of packet buffers) and starts sending a DATA0 or DATA1 PID
according to USB_EPnR bit DTOG_TX. When the PID is completed, the first byte from the
word, read from buffer memory, is loaded into the output shift register to be transmitted on
the USB bus. After the last data byte is transmitted, the computed CRC is sent. If the
addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the
data packet, according to STAT_TX bits in the USB_EPnR register.
...
OUT and SETUP packets (data reception)
These two tokens are handled by the USB peripheral more or less in the same way; the
differences in the handling of SETUP packets are detailed in the following paragraph about
control transfers. When receiving an OUT/SETUP PID, if the address matches a valid
endpoint, the USB peripheral accesses the contents of the ADDRn_RX and COUNTn_RX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of the ADDRn_RX is stored directly in its internal register ADDR. While COUNT is
now reset and the values of BL_SIZE and NUM_BLOCK bit fields, which are read within
COUNTn_RX content are used to initialize BUF_COUNT, an internal 16 bit counter, which is
used to check the buffer overrun condition (all these internal registers are not accessible by
software). Data bytes subsequently received by the USB peripheral are packed in words
(the first byte received is stored as least significant byte) and then transferred to the packet
buffer starting from the address contained in the internal ADDR register while BUF_COUNT
is decremented and COUNT is incremented at each byte transfer. When the end of DATA
packet is detected, the correctness of the received CRC is tested and only if no errors
occurred during the reception, an ACK handshake packet is sent back to the transmitting
host.
...
so the stm32 hardware does much more than that, literally for stuff going to the host just leave data in the 'IN' mailbox and hardware sends it.
then for 'OUT' data to device, it is in the 'OUT' mailbox
but i think callbacks are still relevant, in the form of 'you have mail' and 'mail sent' interrupts.
e.g. for 'IN' (i.e. host wants data') we'd put the 1st 'packet' of data in the 'IN', mailbox, once that is sent.
the core (in fact usb core) interrupts and says 'mail sent', so we'd place the next 'bucket' of data to be sent