HSI, HSE, PLL ???
Posted: Sat Jul 20, 2024 5:26 pm
Is there an good and understandable explanation, how clock system is working?
From reference manual RM0444 (STM32G0B1CBT6):
So HSISYS = 16 MHz and SYSCLK = 16 MHz.
But in generic_clock.c I see:
Is PLLCLK = PLLRCLK?
Inside generic_clock.c I find:
So PLLRCLK, PLLQCLK and PLLRCLK = 64 MHz (16 MHz / 1 * 8 / 2) ?
But how can SYSCLK be 16 MHz?
And what if I want to use HSE?
Crystal is 8 MHz - half of HSI . Would millis() work with half the speed?
From reference manual RM0444 (STM32G0B1CBT6):
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3.3.4 FLASH read access latency
After power reset, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait state (WS) is
configured in the FLASH_ACR register.
When wakeup from Standby, the HCLK clock frequency is 16 MHz in Range 1 and 0 wait
state (WS) is configured in the FLASH_ACR register.
Code: Select all
5.2 Clocks
The HSISYS is used as system clock source after startup from reset, with the division by 1
(producing HSI16 frequency).

But in generic_clock.c I see:
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK
Inside generic_clock.c I find:
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
RCC_OscInitStruct.PLL.PLLN = 8;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
But how can SYSCLK be 16 MHz?
And what if I want to use HSE?
Crystal is 8 MHz - half of HSI . Would millis() work with half the speed?