nucleo-H743Zi clock misconfiguration. V.2.0.0.
Posted: Mon May 10, 2021 7:22 pm
File: variant_NUCLEO_H743ZI.cpp
Having hard time to make SPI working on nucleo-H743ZI2, noticed that
clock to SPI123 selector default settings is PLL1-Q1, same time divider set to 2.
Max freq. for this line is 200 Mhz, Table 59. Kernel clock distribution overview RM0433. Divider 2 means 480 MHz
Having hard time to make SPI working on nucleo-H743ZI2, noticed that
clock to SPI123 selector default settings is PLL1-Q1, same time divider set to 2.
Code: Select all
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 120;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;