Writing to GPIOs on two different ports at the same time?

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dannyf
Posts: 447
Joined: Sat Jul 04, 2020 7:46 pm

Re: Writing to GPIOs on two different ports at the same time?

Post by dannyf »

It is impossible and unnecessary to have your original ask ("changing pin states on different ports at the same time").

It is possible and depending on the spec, to change the pin state on different ports sufficiently fast.

Understanding the timing on the software is key
trimarco232
Posts: 34
Joined: Wed Jul 12, 2023 11:09 am
Answers: 1

Re: Writing to GPIOs on two different ports at the same time?

Post by trimarco232 »

dannyf wrote: Wed Sep 20, 2023 7:18 pm
Is there an easy way to synchronize writes to GPIOs on two different ports so they happen at the same time?
unless in some highly-specialized cases, the answer is no.
two ways that I can think of:
1. you can use timer output compares to output up to 4 pin states. those OC pins can be on different ports.
2. you can use analog comparators to output to different pins / on different ports.
in both cases, the number of pins you can output to is highly limited.
Hi , you can synchronize the timers , so the number of pins is near to bit unlimited
ag123
Posts: 1898
Joined: Thu Dec 19, 2019 5:30 am
Answers: 30

Re: Writing to GPIOs on two different ports at the same time?

Post by ag123 »

Code: Select all

uint16_t set_bits   = 0b0011001100110011;
uint16_t reset_bits = 0b1100110011001100;
GPIOx->regs->BSRR |= set_bits | ( reset_bits << 16 );
https://gist.github.com/iwalpola/6c36c9 ... 0a118571ca
oh ok that's the same port, but you have got 16 bits / pins ;)

anything more complicated, e.g. latching a large address bus, it may take the addressable peripheral to have chip select functions to latch the bits or a shift register.

I've got a harder problem to solve, if you use a non-usb chip and add
https://www.onsemi.com/pdf/datasheet/usb1t11a-d.pdf
and that the data to usb is transmitting via SPI and DMA to usbb1t11amx, how to toggle /SE0 (pull both D+ / D- to 0) at exactly the right bit / time synchronized to SPI and DMA so that that bit will land and lift exactly where the EOP (end of packet) /SE0 chip/bit is required to end a USB packet at 12 Mhz, clocked to the slot like hardware timing. the specs for that /SE0 chip is 160 ns - 175 ns exactly (5.7 mhz - 6.2 mhz signalling speeds and exactness) and need to start exactly after the last data bit.
(^ for this I think it may be possible to cheat a bit using a hw timer, but that then it requires the timer to sync against DMA and SPI)
i.e. how to make a usb state machine engine with just a none-usb chip, and also at the receive end as well and at 12 Mhz full speed in pure firmware. -
I think the *receive* part may be harder to do, e.g how to sync with the SYNC field from SPI and DMA, and 'auto lock' to sync pattern
(0b01010100) 0x54 and 'automatically' buffer that data frame after SYNC with SPI and DMA. i.e. detect that SYNC byte, and after that all data belongs to the USB PDU (protocol data unit) up to EOP (/SE0 chip/bit) of 160 ns - 175 ns exactly
the *sync* is possibly very hard as we are trying to do *clock recovery* by achieving sync to (0b01010100) 0x54 and make the clock sync to a 12 mhz clock at the source, and to 'auto sync' SYNC patterns i.e. software PLL
this is deemed *impossible* by some
if that is possible, then it is possible to do usb Full speed (12 mbps) with any stm32 *without usb*

full usb specs there
https://www.usb.org/document-library/us ... cification
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